1. Field of the Invention
The invention generally relates to a semiconductor device and method of manufacture and, more particularly, to a complementary metal-oxide-semiconductor (CMOS) device that includes an etch stop layer with a selectively varying thickness.
2. Background Description
As semiconductor devices continue to evolve towards higher densities of circuit elements, the performance of materials used for the devices becomes more critical to overall performance, such as charge carrier mobility. CMOS devices fabricated on substrates having a thin strained silicon (Si) layer on a relaxed SiGe buffer layer exhibit substantially higher electron and hole mobility in strained Si layers than in bulk silicon layers. Furthermore, metal oxide semiconductor field effect transistors (MOSFETs) with strained Si channels exhibit enhanced device performance compared to devices fabricated in conventional (unstrained) silicon substrates. Unfortunately, however, as Ge concentrations increase to a level required to enhance performance of p-channel field effect transistors, so does defect density.
Another approach for achieving performance enhancement involves imparting local mechanical stresses. Electron mobility and, thus, n-channel field effect transistor (nFET) performance may be improved by imparting tensile stress either along (i.e., parallel to) the direction of a current flow and/or orthogonal to the direction of current flow. Additionally, hole mobility and, thus, p-channel field effect transistor (PFET) performance, may be enhanced by imparting compressive stress parallel to the direction of current flow and tensile stress perpendicular to the direction of current flow.
Etch stop films may be applied to impart tensile and compressive stresses. For example, a tensile stress may be imparted to an NFET channel by applying a tensile etch stop film. A compressive stress may be imparted to a pFET channel by applying a compressive etch stop film. However, such an approach has drawbacks. In particular, the compressive film degrades NFET performance, while the tensile film degrades pFET performance.
Furthermore, although etch stop films may be configured to impart significant stresses, relatively thick films are required as the stress transferred is proportional to film thickness. Problematically, as film thickness increases, voids are likely to form in the film. This is especially true in dense structures, such as cache or SRAM cells, where gates are very closely spaced, e.g., at a minimum pitch. During contact etching, such voids may open and fill with contact metal. As the voids run parallel to the gates, the voids filled with contact metal may cause contact shorts, thereby preventing proper circuit functionality.
The invention is directed to overcoming one or more of the problems as set forth above.